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d a t a sh eet product speci?cation supersedes data of 2002 mar 01 2003 jun 25 integrated circuits 74alvc573 octal d-type transparent latch; 3-state
2003 jun 25 2 philips semiconductors product speci?cation octal d-type transparent latch; 3-state 74alvc573 features wide supply voltage range from 1.65 to 3.6 v complies with jedec standards: jesd8-7 (1.65 to 1.95 v) jesd8-5 (2.3 to 2.7 v) jesd8b/jesd36 (2.7 to 3.6 v). 3.6 v tolerant inputs and outputs cmos low power consumption direct interface with ttl levels (2.7 to 3.6 v) power-down mode latch-up performance exceeds 250 ma esd protection: hbm eia/jesd22-a114-a exceeds 2000 v mm eia/jesd22-a115-a exceeds 200 v. description the 74alvc573 is a high-performance, low-power, low-voltage, si-gate cmos device and superior to most advanced cmos compatible ttl families. the 74alvc573 is an octal d-type transparent latch featuring separate d-type inputs for each latch and 3-state outputs for bus oriented applications. a latch enable (le) input and an output enable ( oe) input are common to all internal latches. the 74alvc573 consists of eight d-type transparent latches with 3-state true outputs. when le is high, data at the dn inputs enters the latches. in this condition the latches are transparent, i.e. a latch output will change state each time its corresponding d-input changes. when le is low the latches store the information that was present at the d-inputs a set-up time preceding the high-to-low transition of le. when oe is low, the contents of the 8 latches are available at the outputs. when oe is high, the outputs go to the high-impedance off-state. operation of the oe input does not affect the state of the latches. the 74alvc573 is functionally identical to the 74alvc373, but the has a different pin arrangement. quick reference data gnd = 0 v; t amb =25 c. notes c pd is used to determine the dynamic power dissipation (p d in m w). p d =c pd v cc 2 f i n+ s (c l v cc 2 f o ) where: f i = input frequency in mhz; f o = output frequency in mhz; c l = output load capacitance in pf; v cc = supply voltage in volts; n = total load switching outputs; s (c l v cc 2 f o ) = sum of the outputs. 1. the condition is v i = gnd to v cc . symbol parameter conditions typical unit t phl /t plh propagation delay input dn to output qn v cc = 1.8 v; c l = 30 pf; r l =1k w 2.5 ns v cc = 2.5 v; c l = 30 pf; r l = 500 w 2.0 ns v cc = 2.7 v; c l = 50 pf; r l = 500 w 2.3 ns v cc = 3.3 v; c l = 50 pf; r l = 500 w 2.2 ns c i input capacitance 3.5 pf c pd power dissipation capacitance per buffer v cc = 3.3 v; notes and 1 outputs enabled 37 pf outputs disabled 7 pf
2003 jun 25 3 philips semiconductors product speci?cation octal d-type transparent latch; 3-state 74alvc573 function table see note 1 note 1. h = high voltage level; a) h = high voltage level one set-up time prior to the high-to-low le transition; b) l = low voltage level; c) l = low voltage level one set-up time prior to the high-to-low le transition; d) z = high-impedance off-state. ordering information operating modes input internal latch output oe le dn qn enable and read register (transparent mode) lhlll lhhhh latch and read register l l l l l llhhh latch register and disable outputs hlllz hlhhz type number package temperature range pins package material code 74ALVC573D - 40 to +85 c 20 so20 plastic sot163-1 74alvc573pw - 40 to +85 c 20 tssop20 plastic sot360-1 74alvc573bq - 40 to +85 c 20 dhvqfn20 plastic sot764-1 pinning pin symbol description 1 oe output enable input (active low) 2 d0 data input 3 d1 data input 4 d2 data input 5 d3 data input 6 d4 data input 7 d5 data input 8 d6 data input 9 d7 data input 10 gnd ground (0 v) 11 le latch enable input (active high) 12 q7 3-state latch output 13 q6 3-state latch output 14 q5 3-state latch output 15 q4 3-state latch output 16 q3 3-state latch output 17 q2 3-state latch output 18 q1 3-state latch output 19 q0 3-state latch output 20 v cc supply voltage pin symbol description
2003 jun 25 4 philips semiconductors product speci?cation octal d-type transparent latch; 3-state 74alvc573 handbook, halfpage oe d0 d1 d2 d3 573 d4 d5 d6 d7 gnd v cc q0 q1 q2 q4 q5 q3 q6 q7 le 1 2 3 4 5 6 7 8 9 10 11 12 20 19 18 17 16 15 14 13 mna806 fig.1 pin configuration so20 and tssop20. handbook, halfpage 1 2 3 4 5 6 7 8 9 d0 d1 d2 d3 d4 d5 d6 d7 19 18 17 16 15 14 13 12 q1 q0 q2 q3 q4 q5 q6 q7 20 oe v cc 10 11 gnd top view le gnd (1) mna979 fig.2 pin configuration dhvqfn20. (1) the die substrate is attached to this pad using conductive die attach material. it can not be used as a supply pin or input. fig.3 logic symbol. handbook, halfpage mna807 d0 d1 d2 d3 d4 d5 d6 d7 le oe q0 q1 q2 q3 q4 q5 q6 q7 1 11 12 13 14 15 16 17 18 19 9 8 7 6 5 4 3 2 handbook, halfpage mna808 12 13 14 15 16 17 18 11 c1 1 en1 1d 19 9 8 7 6 5 4 3 2 fig.4 iec logic symbol.
2003 jun 25 5 philips semiconductors product speci?cation octal d-type transparent latch; 3-state 74alvc573 handbook, halfpage mna809 3-state outputs latch 1 to 8 q0 q1 q2 q3 q4 q5 q6 q7 12 13 14 15 16 17 18 19 d0 d1 d2 d3 d4 d5 d6 d7 le oe 9 11 1 8 7 6 5 4 3 2 fig.5 function diagram. handbook, halfpage q le d le le le mna692 fig.6 logic diagram (one latch). handbook, full pagewidth mna810 q4 d4 d le q q3 d3 d le q q2 d2 d le q q1 d1 d le le le q q0 d0 d latch 1 latch 2 latch 3 latch 4 latch 5 q le oe le le le le q5 d5 d le q latch 6 le q6 d6 d le q latch 7 le q7 d7 d le q latch 8 le fig.7 logic diagram.
2003 jun 25 6 philips semiconductors product speci?cation octal d-type transparent latch; 3-state 74alvc573 recommended operating conditions limiting values in accordance with the absolute maximum rating system (iec 60134); voltages are referenced to gnd (ground = 0 v). notes 1. the input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. when v cc = 0 v (power-down mode), the output voltage can be 3.6 v in normal operation. 3. for so20 packages: above 70 c the value of p tot derates linearly with 8 mw/k. a) for tssop20 packages: above 60 c the value of p tot derates linearly with 5.5 mw/k. b) for dhvqfn20 packages: above 60 c the value of p tot derates linearly with 4.5 mw/k. symbol parameter conditions min. max. unit v cc supply voltage 1.65 3.6 v v i input voltage 0 3.6 v v o output voltage v cc = 1.65 to 3.6 v; enable mode 0 v cc v v cc = 1.65 to 3.6 v; disable mode 0 3.6 v v cc = 0 v; power-down mode 0 3.6 v t amb operating ambient temperature - 40 +85 c t r , t f input rise and fall times v cc = 1.65 to 2.7 v 0 20 ns/v v cc = 2.7 to 3.6 v 0 10 ns/v symbol parameter conditions min. max. unit v cc supply voltage - 0.5 +4.6 v i ik input diode current v i <0 -- 50 ma v i input voltage - 0.5 +4.6 v i ok output diode current v o >v cc or v o <0 - 50 ma v o output voltage enable mode; notes 1 and 2 - 0.5 v cc + 0.5 v disable mode - 0.5 +4.6 v power-down mode; note 2 - 0.5 +4.6 v i o output source or sink current v o =0tov cc - 50 ma i cc , i gnd v cc or gnd current - 100 ma t stg storage temperature - 65 +150 c p tot power dissipation t amb = - 40 to +85 c; note 3 - 500 mw
2003 jun 25 7 philips semiconductors product speci?cation octal d-type transparent latch; 3-state 74alvc573 dc characteristics at recommended operating conditions; voltages are referenced to gnd (groun d=0v). notes 1. all typical values are measured at v cc = 3.3 v and t amb =25 c. 2. for transceivers, the parameter i oz includes the input leakage current. symbol parameter test conditions min. typ. (1) max. unit other v cc (v) t amb = - 40 to +85 c v ih high-level input voltage 1.65 to 1.95 0.65 v cc -- v 2.3 to 2.7 1.7 -- v 2.7 to 3.6 2 -- v v il low-level input voltage 1.65 to 1.95 -- 0.35 v cc v 2.3 to 2.7 -- 0.7 v 2.7 to 3.6 -- 0.8 v v ol low-level output voltage v i =v ih or v il i o = 100 m a 1.65 to 3.6 -- 0.2 v i o = 6 ma 1.65 -- 0.3 v i o = 12 ma 2.3 -- 0.4 v i o = 18 ma 2.3 -- 0.6 v i o = 12 ma 2.7 -- 0.4 v i o = 18 ma 3.0 -- 0.4 v i o = 24 ma 3.0 -- 0.55 v v oh high-level output voltage v i =v ih or v il i o = - 100 m a 1.65 to 3.6 v cc - 0.2 -- v i o = - 6 ma 1.65 1.25 -- v i o = - 12 ma 2.3 1.8 -- v i o = - 18 ma 2.3 1.7 -- v i o = - 12 ma 2.7 2.2 -- v i o = - 18 ma 3.0 2.4 -- v i o = - 24 ma 3.0 2.2 -- v i li input leakage current v i = 3.6 v or gnd 3.6 - 0.1 5 m a i oz 3-state output off-state current v i =v ih or v il ; v o = 3.6 v or gnd; note 2 1.65 to 3.6 - 0.1 10 m a i off power off leakage current v i or v o = 0 to 3.6 v 0.0 - 0.1 10 m a i cc quiescent supply current v i =v cc or gnd; i o =0 3.6 - 0.2 10 m a d i cc additional quiescent supply current per input pin v i =v cc - 0.6 v; i o =0 3.0 to 3.6 - 5 750 m a
2003 jun 25 8 philips semiconductors product speci?cation octal d-type transparent latch; 3-state 74alvc573 ac characteristics note 1. all typical values are measured at t amb =25 c. symbol parameter test conditions min. typ. max. unit waveforms v cc (v) t amb = - 40 to +85 c; see note 1 t phl /t plh propagation delay dn to qn see figs 8 and 12 1.65 to 1.95 1.0 2.5 5.4 ns 2.3 to 2.7 1.0 2.0 3.5 ns 2.7 1.0 2.3 3.6 ns 3.0 to 3.6 1.0 2.2 3.3 ns t phl /t plh propagation delay le to qn see figs 9 and 12 1.65 to 1.95 1.0 2.8 6.0 ns 2.3 to 2.7 1.0 2.1 3.8 ns 2.7 1.0 2.4 3.7 ns 3.0 to 3.6 1.0 2.3 3.3 ns t pzh /t pzl 3-state output enable time oe to qn see figs 10 and 12 1.65 to 1.95 1.5 3.0 6.4 ns 2.3 to 2.7 1.0 2.4 4.5 ns 2.7 1.5 3.0 4.6 ns 3.0 to 3.6 1.0 2.3 4.0 ns t phz /t plz 3-state output disable time oe to qn see figs 10 and 12 1.65 to 1.95 1.5 3.4 7.0 ns 2.3 to 2.7 1.0 2.2 4.4 ns 2.7 1.5 2.8 4.4 ns 3.0 to 3.6 1.0 2.7 4.4 ns t w le pulse with high see figs 9 and 12 1.65 to 1.95 3.8 -- ns 2.3 to 2.7 3.3 -- ns 2.7 3.3 -- ns 3.0 to 3.6 3.3 -- ns t su set-up time dn to le see figs 11 and 12 1.65 to 1.95 0.8 -- ns 2.3 to 2.7 0.8 -- ns 2.7 0.8 -- ns 3.0 to 3.6 0.8 -- ns t h hold time dn to le see figs 11 and 12 1.65 to 1.95 0.8 -- ns 2.3 to 2.7 0.8 -- ns 2.7 0.8 -- ns 3.0 to 3.6 0.7 -- ns
2003 jun 25 9 philips semiconductors product speci?cation octal d-type transparent latch; 3-state 74alvc573 ac waveforms handbook, halfpage mna811 dn input qn output t phl t plh gnd v i v m v m v oh v ol fig.8 input dn to output qn propagation delay times. v cc input v m v i t r =t f 1.65 to 1.95 v v cc 2.0 ns 0.5 v cc 2.3 to 2.7 v v cc 2.0 ns 0.5 v cc 2.7 v 2.7 v 2.5 ns 1.5 v 3.0 to 3.6 v 2.7 v 2.5 ns 1.5 v handbook, full pagewidth mna812 le input qn output t phl t plh t w 1/f max v m v oh v i gnd v ol v m fig.9 latch enable (le) input pulse width and latch enable input to output (qn) propagation delays. v cc v m input v i t r =t f 1.65 to 1.95 v 0.5 v cc v cc 2.0 ns 2.3 to 2.7 v 0.5 v cc v cc 2.0 ns 2.7 v 1.5 v 2.7 v 2.5 ns 3.0 to 3.6 v 1.5 v 2.7 v 2.5 ns
2003 jun 25 10 philips semiconductors product speci?cation octal d-type transparent latch; 3-state 74alvc573 handbook, full pagewidth mna813 t plz t phz outputs disabled outputs enabled v y v x outputs enabled qn output low-to-off off-to-low qn output high-to-off off-to-high oe input v ol v oh v cc v i v m gnd gnd t pzl t pzh v m v m fig.10 3-state enable and disable times. v cc input v m v x v y v i t r =t f 1.65 to 1.95 v v cc 2.0 ns 0.5 v cc v ol + 0.15 v v oh - 0.15 v 2.3 to 2.7 v v cc 2.0 ns 0.5 v cc v ol + 0.15 v v oh - 0.15 v 2.7 v 2.7 v 2.5 ns 1.5 v v ol + 0.3 v v oh - 0.3 v 3.0 to 3.6 v 2.7 v 2.5 ns 1.5 v v ol + 0.3 v v oh - 0.3 v v ol and v oh are typical output voltage drop that occur with the output load.
2003 jun 25 11 philips semiconductors product speci?cation octal d-type transparent latch; 3-state 74alvc573 handbook, full pagewidth mna814 t h t su t h t su v m v m v i gnd v i gnd le input dn input fig.11 data set-up and hold times for dn input to le input. the shaded areas indicate when the input is permitted to change for predictable output performance. v cc v m input v i t r =t f 1.65 to 1.95 v 0.5 v cc v cc 2.0 ns 2.3 to 2.7 v 0.5 v cc v cc 2.0 ns 2.7 v 1.5 v 2.7 v 2.5 ns 3.0 to 3.6 v 1.5 v 2.7 v 2.5 ns handbook, full pagewidth v ext v cc v i v o mna616 d.u.t. c l r t r l r l pulse generator fig.12 load circuitry for switching times. definitions for test circuit: r l = load resistor. c l = load capacitance including jig and probe capacitance. r t = termination resistance should be equal to the output impedance z o of the pulse generator. v cc v i c l r l v ext t plh /t phl t pzh /t phz t pzl /t plz 1.65 to 1.95 v v cc 30 pf 1 k w open gnd 2 v cc 2.3 to 2.7 v v cc 30 pf 500 w open gnd 2 v cc 2.7 v 2.7 v 50 pf 500 w open gnd 6 v 3.0 to 3.6 v 2.7 v 50 pf 500 w open gnd 6 v
2003 jun 25 12 philips semiconductors product speci?cation octal d-type transparent latch; 3-state 74alvc573 package outlines unit a max. a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p q z y w v q references outline version european projection issue date iec jedec jeita mm inches 2.65 0.3 0.1 2.45 2.25 0.49 0.36 0.32 0.23 13.0 12.6 7.6 7.4 1.27 10.65 10.00 1.1 1.0 0.9 0.4 8 0 o o 0.25 0.1 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 1.1 0.4 sot163-1 10 20 w m b p detail x z e 11 1 d y 0.25 075e04 ms-013 pin 1 index 0.1 0.012 0.004 0.096 0.089 0.019 0.014 0.013 0.009 0.51 0.49 0.30 0.29 0.05 1.4 0.055 0.419 0.394 0.043 0.039 0.035 0.016 0.01 0.25 0.01 0.004 0.043 0.016 0.01 0 5 10 mm scale x q a a 1 a 2 h e l p q e c l v m a (a ) 3 a so20: plastic small outline package; 20 leads; body width 7.5 mm sot163-1 99-12-27 03-02-19
2003 jun 25 13 philips semiconductors product speci?cation octal d-type transparent latch; 3-state 74alvc573 unit a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 6.6 6.4 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.5 0.2 8 0 o o 0.13 0.1 0.2 1 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 sot360-1 mo-153 99-12-27 03-02-19 w m b p d z e 0.25 110 20 11 pin 1 index q a a 1 a 2 l p q detail x l (a ) 3 h e e c v m a x a y 0 2.5 5 mm scale tssop20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm sot360-1 a max. 1.1
2003 jun 25 14 philips semiconductors product speci?cation octal d-type transparent latch; 3-state 74alvc573 terminal 1 index area 0.5 1 a 1 e h b unit y e 0.2 c references outline version european projection issue date iec jedec jeita mm 4.6 4.4 d h 3.15 2.85 y 1 2.6 2.4 1.15 0.85 e 1 3.5 0.30 0.18 0.05 0.00 0.05 0.1 dimensions (mm are the original dimensions) sot764-1 mo-241 - - - - - - 0.5 0.3 l 0.1 v 0.05 w 0 2.5 5 mm scale sot764-1 dhvqfn20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body 2.5 x 4.5 x 0.85 mm a (1) max. a a 1 c detail x y y 1 c e l e h d h e e 1 b 29 19 12 11 10 1 20 x d e c b a terminal 1 index area a c c b v m w m e (1) note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. d (1) 02-10-17 03-01-27
2003 jun 25 15 philips semiconductors product speci?cation octal d-type transparent latch; 3-state 74alvc573 soldering introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering can still be used for certain surface mount ics, but it is not suitable for fine pitch smds. in these situations reflow soldering is recommended. re?ow soldering reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical reflow peak temperatures range from 215 to 270 c depending on solder paste material. the top-surface temperature of the packages should preferably be kept: below 220 c (snpb process) or below 245 c (pb-free process) C for all bga and ssop-t packages C for packages with a thickness 3 2.5 mm C for packages with a thickness < 2.5 mm and a volume 3 350 mm 3 so called thick/large packages. below 235 c (snpb process) or below 260 c (pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm 3 so called small/thin packages. moisture sensitivity precautions, as indicated on packing, must be respected at all times. wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was specifically developed. if wave soldering is used the following conditions must be observed for optimal results: use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 c or 265 c, depending on solder material applied, snpb or pb-free respectively. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. manual soldering fix the component by first soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
2003 jun 25 16 philips semiconductors product speci?cation octal d-type transparent latch; 3-state 74alvc573 suitability of surface mount ic packages for wave and re?ow soldering methods notes 1. for more detailed information on the bga packages refer to the (lf)bga application note (an01026); order a copy from your philips semiconductors sales office. 2. all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . 3. these transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 c 10 c measured in the atmosphere of the reflow oven. the package body peak temperature must be kept as low as possible. 4. these packages are not suitable for wave soldering. on versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. on versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 5. if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. 6. wave soldering is suitable for lqfp, tqfp and qfp packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 7. wave soldering is suitable for ssop, tssop, vso and vssop packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. package (1) soldering method wave reflow (2) bga, lbga, lfbga, sqfp, ssop-t (3) , tfbga, vfbga not suitable suitable dhvqfn, hbcc, hbga, hlqfp, hsqfp, hsop, htqfp, htssop, hvqfn, hvson, sms not suitable (4) suitable plcc (5) , so, soj suitable suitable lqfp, qfp, tqfp not recommended (5)(6) suitable ssop, tssop, vso, vssop not recommended (7) suitable
2003 jun 25 17 philips semiconductors product speci?cation octal d-type transparent latch; 3-state 74alvc573 data sheet status notes 1. please consult the most recently issued data sheet before initiating or completing a design. 2. the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the latest information is available on the internet at url http://www.semiconductors.philips.com. 3. for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. level data sheet status (1) product status (2)(3) definition i objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. ii preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?cation (cpcn). definitions short-form specification ? the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition ? limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information ? applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. disclaimers life support applications ? these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes ? philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production), relevant changes will be communicated via a customer product/process change notification (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
2003 jun 25 18 philips semiconductors product speci?cation octal d-type transparent latch; 3-state 74alvc573 notes
2003 jun 25 19 philips semiconductors product speci?cation octal d-type transparent latch; 3-state 74alvc573 notes
? koninklijke philips electronics n.v. 2003 sca75 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. philips semiconductors C a worldwide company contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales of?ces addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . printed in the netherlands 613508/02/pp 20 date of release: 2003 jun 25 document order number: 9397 750 11268

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